According to a report from Zhitong Finance APP, the UBS Asia semiconductor team has released its latest industry report titled "Asia Semis Pulse," identifying four simultaneously accelerating themes: TSMC's A14 angstrom-level process construction timeline being pulled forward, MediaTek opening a second growth curve through Google TPU and new ASIC projects, silicon capacitors becoming the new choke point in AI packaging, and silicon wafers entering their third upcycle. The core conclusion of the report is that cloud AI demand is pushing every segment of the semiconductor upstream supply chain into simultaneous capacity expansion — from 1.4nm-class fabs to the most inconspicuous passive components.

A14 Accelerates: Baoshan Equipment Move-In, Zhongke Expansion Pulled Forward

UBS states that TSMC (TSM.US) is further accelerating construction of its most advanced capacity: the new A14 node will first begin equipment move-in at Baoshan Fab 20 in the second half of 2026, while the originally planned expansion at Zhongke Fab 25 is being pulled forward to support larger capacity scale when mass production begins in 2028. UBS estimates that by the end of 2028, TSMC could build approximately 60,000 wafers per month of A14 capacity, higher than N2's installed capacity of 30,000 to 40,000 wafers per month over the same period. This assessment is corroborated by publicly available information from Taiwan's supply chain. Taiwan media reported on September 25 that A14 has already begun trial production at Hsinchu Baoshan Fab 20 and Zhongke Fab 25, used to evaluate node feasibility and allow customers to understand in advance how their designs perform in a mass production environment. Because trial production progress has exceeded expectations, the timeline has been moved forward; according to the plan, A14 will enter risk production in 2027 and mass production in Taiwan in 2028. The P3 area of Baoshan Fab 20 obtained its usage permit in the second quarter and began equipment move-in in September, with trial production expected in the first quarter of 2027; the P1 area of Zhongke Fab 25, the main mass production site, is expected to be completed before April 2027, with P2 through P4 being rushed simultaneously. Combined A14 capacity from both fabs is approximately 60,000 to 70,000 wafers per month. In terms of specifications, A14 offers a 10% to 15% speed improvement at the same power consumption compared to N2, or a 25% to 30% power reduction at the same frequency, with logic density increased by more than 20%. It adopts second-generation nanosheet transistors and NanoFlex Pro standard cells, while lithography still uses Low-NA EUV, with High-NA not expected until around the 1nm node. On the competitive side, UBS highlights two comparisons: Intel (INTC.US) targets 14A mass production in 2028 and will release PDK 1.0 later this year; Samsung Foundry's SF1.4 appears delayed to 2029 for mass production due to yield challenges. Intel Foundry head Naga Chandrasekaran has previously publicly stated that the performance gap between 14A and TSMC's A14 is expected to be within 5%, and plans to begin risk production in the second half of 2027. In other words, the two companies will collide head-on in the angstrom era during 2027 to 2028, while Samsung falls behind.

Capital Expenditure Raised: Breaking $100 Billion in 2028

Based on larger-scale expansion of N3 and N2 as well as A14's faster ramp, UBS has raised its capital expenditure forecasts for TSMC in 2027 and 2028 from $80 billion and $95 billion to $90 billion and $105 billion. This is the most direct numerical upward revision in this report. On the capacity side, institutional estimates suggest TSMC's 2nm monthly capacity could reach 90,000 to 100,000 wafers by the end of this year and rise to 130,000 to 140,000 wafers in 2027, while Southern Taiwan Science Park's 3nm capacity will be approximately 170,000 to 180,000 wafers in the fourth quarter of this year and could exceed 200,000 wafers next year — meaning 2027 will see the rare situation of N3, N2/A16, and A14 all expanding and trial-producing simultaneously across three generations. Digitimes notes that TSMC's 3nm, 2nm, and CoWoS advanced packaging capacity continues to be in short supply. As Amazon AWS and MediaTek each increase wafer starts due to their in-house AI chips and Google TPU orders, TSMC has readjusted its advanced capacity allocation.

MediaTek: TPU v9 Locked In, 20x Growth in Two Years

The second major theme in the report is MediaTek. UBS says its view on the EMIB-T packaging solution for TPU v9 is turning more positive: substrate maker Ibiden's yields are improving, and Unimicron and Shinko Electric are increasing mass production support for sub-2nm TPU v9; if TPU v9 demand exceeds 4 million units in 2029, MediaTek is in discussions with TSMC to add CoWoS advanced packaging in addition to EMIB-T. It is understood that TPU v9 will simultaneously adopt TSMC's CoWoS-L and Intel's EMIB-T. After the front-end and back-end supply model changes, TSMC has slightly adjusted MediaTek's 3nm and 2nm capacity arrangements. The quantitative portion is even more striking. UBS estimates that Google TPU-related sales will jump from $2.1 billion in 2026 to $18 billion in 2027, $43.5 billion in 2028, $52.5 billion in 2029, and reach $60 billion in 2030 — in other words, 20x growth in two years. TPU business as a share of MediaTek's revenue will accordingly rise from 10% in 2026 to 65% in 2028 (68% and 69% in 2029 and 2030), while TPU business EPS contribution will expand from NT$8.1 to NT$291.4 in 2028 and NT$402 in 2030. Driving this estimate are new projects beyond TPU. UBS says MediaTek is in talks on two new ASIC programs, expected to be finalized in the coming months, with combined revenue opportunity of up to $10 billion to $15 billion: first, SpaceX's Dojo 3, using TSMC's 2nm and wafer-level system (SoW) packaging, and possibly partnering with NVIDIA to provide NVLink Fusion; second, Tesla AI6, used for advanced driver assistance and robotics, planned to be initially produced at Intel fabs before later transitioning to Terafab. This logic was already presented by UBS in a separate MediaTek report on September 24: reiterating Buy, with a target price raised from NT$6,500 to NT$7,300, and predicting MediaTek's 2027 revenue will grow 85% year-over-year to NT$1.25 trillion, then increase by approximately 70% to NT$2.14 trillion in 2028, with EPS reaching NT$363.36 in 2028; UBS emphasizes that its 2028 EPS estimate is 44% above market consensus. This pulse report serves as an industry-side footnote to that assessment.

Silicon Capacitors: The New Choke Point in AI Packaging

The third major theme is silicon capacitors. UBS's logic is that as AI and HPC packaging sizes continue to grow and power consumption rises, power integrity becomes a key bottleneck, making silicon capacitors a critical component within the package. In the past, silicon capacitors basically existed only in TSMC's CoWoS and interposer ecosystem, but in the coming years they will expand industry-wide with the advanced packaging expansion of Intel EMIB and OSAT companies like ASE; UBS estimates that non-TSMC silicon capacitor demand could grow to 40,000 to 50,000 wafers per month by 2028 to 2029. Beneficiaries include Powerchip Semiconductor Manufacturing Corp (PSMC), which has already passed Intel validation and begun shipping, and United Microelectronics Corp (UMC), joining in 2028 to 2029, both working closely with AP Memory Technology. Samsung Electro-Mechanics also recently announced capacity expansion for silicon capacitors to supply Intel EMIB. The tightness of supply and demand has been quantified by multiple parties. A Morgan Stanley report estimates that as of June this year, the global silicon capacitor shortage rate was as high as 57%, and a structural shortage may persist for the next three years, with gaps of 16% and 11% in 2027 and 2028 respectively. Industry-side capacity expansion and long-term contracts are equally dense: Samsung Electro-Mechanics announced in May a long-term silicon capacitor supply contract worth 1.557 trillion Korean won (approximately $1.035 billion), with an execution period from January 2027 to December 2028, equivalent to 13.8% of its 2025 revenue; analog device giant Analog Devices (ADI) acquired silicon capacitor maker Empower Semiconductor for $1.5 billion, with the deal completed in July. Such components must be incorporated at the packaging design stage and undergo at least two years of reliability verification. Once customers pass certification, they are unlikely to switch. The company plans to expand 12-inch fab silicon capacitor monthly capacity three to four times in the second half of 2027; UMC, meanwhile, says its advanced packaging business already has more than ten customers and will expand to more than 35 new design wins next year. Demand-side certainty comes from two AI leaders: NVIDIA's Rubin architecture has already made embedded silicon capacitors standard, and Intel plans to begin large-scale adoption of silicon capacitors in 2027 to enhance EMIB performance. AP Memory's results have already validated the trend — in the second quarter of 2026, consolidated revenue was NT$2.36 billion, up 78% year-over-year, of which stacked silicon capacitors (S-SiCap) contributed NT$640 million, up 273% year-over-year, accounting for 27% of revenue. However, Business Weekly also points out a ceiling: compared with mature-node foundry for processes above 28nm with annual output value of over $70 billion, this year's global silicon capacitor output value is only about $2.3 billion, not yet large enough to change capacity allocation and profit structure; if silicon capacitors can only ever be attached next to AI chips, their ceiling will be locked by advanced packaging capacity.

Silicon Wafers: The Third Upcycle

The fourth major theme is silicon wafers. UBS, citing Taiwan media reports, says GlobalWafers is negotiating a new round of approximately 8% price increases with customers; if confirmed, this would be its second round after raising prices by about 10% for some 6-inch and 8-inch customers in the second quarter (effective in the second half of 2026). UBS judges that for new capacity to come online, meaningful price increases are necessary to resolve supply tightness before 2028. Price increases started in the first half of 2026, and year-over-year increases in 2027 to 2028 could exceed 20%; the report compares 12-inch wafer utilization rates with GlobalWafers' quotations, noting this is the third upcycle after 2017-2018 and 2021-2022. Supply chain validation is equally dense. In May this year, Shin-Etsu Chemical, SUMCO, and GlobalWafers simultaneously issued price increase letters, initiating the second round of price adjustments for the year, with 12-inch standard products raised 5% to 8%, and high-end specialty silicon wafers for AI and HPC seeing increases of 18% to 22%; entering the second half, 6-inch, 8-inch, and 12-inch products saw their first full-size price increases in over three years, starting at 10%. GlobalWafers completed approximately 10% price increases in the first half and implemented them in the second half. The company confirmed it is negotiating quotes with other 8-inch customers, with new prices potentially applicable from 2027, and has not yet adjusted 12-inch quotes; GlobalWafers Chairman Hsu Hsiu-Lan stated bluntly that both spot and long-term contract prices have entered an upward channel. Demand-side figures come from SUMCO's estimates: AI servers require 3.8 times the 12-inch silicon wafer demand of general-purpose servers, and at equivalent capacity, HBM consumes 3 times the 12-inch silicon wafers of mainstream DRAM. In 2026, AI-related advanced process silicon wafer monthly demand is expected to exceed 1 million wafers, accounting for more than 10% of global 12-inch total demand. SEMI data shows that in the second quarter of 2026, global silicon wafer shipments grew 7.4% year-over-year and 9.1% quarter-over-quarter, reaching 3,573 million square inches, a near two-year quarterly high, and have now recorded four consecutive quarters of positive year-over-year growth (SEMI, SUMCO).

Conclusion

Looking at these four themes together, UBS's pulse report effectively delivers one judgment: the bottleneck in AI computing power is spreading from "compute chips" to "every supporting segment" — advanced processes need to start production earlier, packaging needs to prepare materials earlier, and the most upstream silicon wafers need to raise prices earlier. The report also identifies two variables that need to be tracked: first, whether TSMC's $105 billion capital expenditure in 2028 can be translated into actual capacity; second, MediaTek's packaging route choice between CoWoS and EMIB-T, which will determine whether it can capture TPU demand beyond 2029.